START=NO_START_THIS_VALUE, BURST=SW, EDGE=RISING, PDN=POWERDOWN
A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur.
| SEL | Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01. |
| CLKDIV | The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. |
| BURST | Burst mode 0 (SW): Conversions are software controlled and require 31 clocks. 1 (BURST): The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that’s in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| PDN | Power down mode 0 (POWERDOWN): The A/D converter is in power-down mode. 1 (POWERED): The A/D converter is operational. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| START | When the BURST bit is 0, these bits control whether and when an A/D conversion is started: 0 (NO_START_THIS_VALUE): No start (this value should be used when clearing PDN to 0). 1 (START_CONVERSION_NOW): Start conversion now. 2 (P2_10): Start conversion when the edge selected by bit 27 occurs on the P2[10] pin. 3 (P1_27): Start conversion when the edge selected by bit 27 occurs on the P1[27] pin. 4 (MAT0_1): Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin. 5 (MAT0_3): Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin. 6 (MAT1_0): Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin. 7 (MAT1_1): Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin. |
| EDGE | This bit is significant only when the START field contains 010-111. In these cases: 0 (RISING): Start conversion on a rising edge on the selected CAP/MAT signal. 1 (FALLLING): Start conversion on a falling edge on the selected CAP/MAT signal. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |